The present disclosure relates to an integrated semiconductor device having semiconductor devices integrated therein, and more particularly to an integrated semiconductor device having a circuit adapted to test whether or not the connection status is appropriate between the semiconductor devices making up the integrated semiconductor device.
The boundary-scan technique is known in related art as a technique for testing whether or not the connection is appropriate between semiconductor chips (hereinafter also referred to as the connection test). The boundary-scan technique has been standardized as the IEEE Standard 1149.1 Standard Test Access Port and Boundary-Scan Architecture. This boundary-scan standard was laid down by the JTAG (Joint Test Action Group).
In the connection test using the boundary-scan technique, an internal circuit for the boundary-scan technique is incorporated in advance into the semiconductor chips under test. This internal circuit is also called a boundary-scan cell and provided for each of the terminals used for connection between the semiconductor chips and external equipment. Then, these semiconductor chips are connected together in daisy chain fashion, and signals are transmitted to and from external equipment by controlling the boundary-scan cells provided therein. As a result, the connection between the semiconductor devices can be tested to determine whether or not the connection is appropriate.
However, the boundary-scan technique uses a boundary-scan cell for each of the terminals of the semiconductor chips, thus resulting in a significantly larger circuit scale.
For this reason, the following technique is known as a traditional technique in relation to the connection test between two semiconductor chips. That is, a testing circuit including a flip-flop and switch is inserted between each of the terminals of the two semiconductor chips and the internal circuit. Then, during testing, the switch status is changed to form a signal path that connects the input and output of each of the flip-flops of the two semiconductor chips in series. In this condition, data is successively supplied to the flip-flops to write the data. Next, the switch status is changed to form a signal path that connects each of the flip-flops of one of the semiconductor device to one of the flip-flops of the other semiconductor device via the associated terminal. This allows for data to be shifted from each of the flip-flops of one of the semiconductor device to one of the flip-flops of the other semiconductor device. Finally, a signal path is formed that connects the input and output of each of the flip-flops of the two semiconductor chips in series to read the data, thus determining whether or not the connection is appropriate between the terminals based on the read data (refer, for example, to Japanese Patent Laid-Open No. 2009-47486 (FIG. 1)).
With such a configuration based on the traditional technique, only a flip-flop and switch adapted to change the signal path are incorporated for each terminal, thus providing a smaller circuit scale than the boundary-scan technique.